1. Field of the Invention
This invention relates to byte shifters for data processing systems, and more particularly, to a novel high speed parallel byte shifter for high speed bus architecture data processing systems.
2. Description of the Prior Art
Shifting of bits, bytes and words of data are necessary functions of modern data processing systems. When data is transferred to or from a main storage unit (MSU), there could be a requirement that the data be shifted right or left more than ninety percent of the time.
The requirement for shifting has not presented a technological problem in the prior art for such shifting has been accomplished in various ways too numerous to review in detail. The most common way to shift both bits and bytes of data is to employ the well-known shift register technique. Data loaded into a shift register can be shifted one register position at a time by clock pulses to sequentially shift each bit of data in the shift register to a new position. While shift registers are effective means to shift a bit one or two positions, as would be required in adders, shift registers become exceedingly complex and slow if employed with bus architecture data processing systems which employ large numbers of bits or bytes in parallel to form a single data word.
When bits of data are stored in one register, they are capable of being transferred in parallel to a second register. If the shift requirements are fixed, the connections between the two registers can also be fixed or hard wired to effect a shift operation. Hard wiring shift operations are well known and have the advantage that shifting is accomplished at high speeds. Hard wiring shift operations are employed in adders.
A variation of hard wire shifting from one register to another is accomplished in a barrel shifter or in a multi-bit shift matrix. Such logic circuits are now commercially available as semiconductor devices or as chips which contain the bit shift matrix lines and some external control circuitry. Such devices provide a plurality of alternative paths connected between a plurality of registers. As the number of shift positions are increased, the number of registers also increase by a factor greater than two. When multi-bit matrix shifters are adapted to shift bytes, not only does the number of registers increase greatly, but the logic for accomodating the shift paths increase greatly and the speed of shifting slows down.
It has been suggested that a source register could be connectable to any one of a plurality of buffer registers, one for each possible shift position, through a matrix or a multiplexer circuit arrangement. This would be equivalent to providing a hard wired transfer once proper selection of the gating circuitry logic is made. Selection would be slow regardless of the logic employed and the requirement for numerous registers and/or complex logic would be expensive.
As employed herein, a data word is comprised of plural bytes and a byte is comprised of plural data bits which includes one parity bit. The text and drawings, by way of example, will refer to a data word having four bytes. Each byte is composed of eight data bits and one parity bit.
Data processing systems which transfer data bytes in parallel also transfer the parity bit in parallel with the data. The parity bit provides means for checking or verifying the most common type of error which is the change of one data bit in the data byte. When the bytes of data are being shifted in parallel, the parity bit error detection does not detect a shift error nor does the parity bit detect that the byte being transferred from the data bus to a byte shifter is, in fact, the byte which should be selected for shifting. After a byte has been selected for shifting from a data bus, it must be returned to the data bus in shifted form. Prior art byte shifters have not treated the problem of byte selection error or shifted byte transfer error which could occur in byte shifters.
Data processing systems which employ data bus architecture also employ input and output registers to present and receive bytes and words of data information on the data bus. Byte shifters must take byte data from the data bus and return it after it has been processed. Even if the byte shifter is operable to effect the proper shift operation on the proper byte, the parity check bit of the data byte cannot be employed as a means to check that the shifted byte in the byte shifter is transferred to the proper input or output register of the data bus. If the byte in the data bus register is not changed by loading a new byte, the old byte which remains unchanged still has a proper parity bit, thus absence of a proper transfer or loading of the new byte is not detected.
It is generally recognized that errors in data processing systems are more likely to occur when data as signals are being transferred between registers. When byte shifters are employed which are not hard wired, the probability of error increases greatly. When byte shifters are employed, which employ complex logic and large number of gates in matrix form, the probability of error also increases. When the speed of operation of the data processing system is very high, the inclusion of complex circuitry not only slows down the operation of the byte shifter, but also increases the probability of data selection errors and data transfer errors.
It would be desirable to provide a high speed byte shifter which is adapted to be connected to a bus architecture high speed data processing system and which either avoids the problems of the prior art or provides a simple economical solution to avoid errors and increase speed of operation.